1. Field of the Invention
The present invention generally relates to SOI-related design methodologies, and more particularly to alternating precharge in dynamic logic SOI circuits for high speed, custom design applications.
2. Description of the Related Art
FIG. 1 illustrates a typical clocked domino-logic gate circuit 1. Reset signal 10 is shown separated from clock signal 20 as is often the case in self-resetting circuits, but those skilled in the art would recognize that these signals 10, 20 may also be tied together. Clock signal 20 often drives bottom NFET stack device 30 instead of top NFET stack device 40, but is connected to NFET stack device 40 in FIG. 1 to be consistent with typical SOI applications.
In bulk CMOS, charge-sharing has a significant impact on the circuit of FIG. 1. Charge sharing occurs when clock signal 20 remains low while input signal 50 pulses high. Under these conditions, intermediate NFET stack node 60 discharges to ground 70. In a subsequent cycle, input signal 50 remains low and clock signal 20 pulses high. During this subsequent clock cycle, charge is shared between the primary node 95 common to PFET device 80, PFET device 85, inverter 90, NFET stack device 40, and NFET stack node 60.
Furthermore, NFET stack node 60 charges to a level of Vddxe2x88x92Vthn, where Vthn is the body-effected threshold voltage of an NFET device, and Vdd 11 is the power supply voltage. At the same time, the primary node 95 temporarily discharges to an intermediate level, the magnitude of which depends on the capacitance ratio between the primary node 95 and NFET stack node 60 and the strength of PFET device 85.
Because of the substantial source and drain capacitance of devices in bulk technologies, it is possible for charge sharing to discharge the primary node 95 sufficiently to cause an unintentional switching of inverter 90. This unintentional switching causes output node 98 to pulse high. Subsequent logic stages will therefore evaluate incorrectly, causing the chip to fail. This is a fundamental disadvantage and defect of this conventional circuit.
Several circuit techniques are applied to bulk circuits to minimize the effects of charge sharing. Increasing the strength of PFET device 85 in FIG. 1 reduces the magnitude of the charge-sharing excursion on the primary node 95. However, increasing the strength of PFET device 85 can significantly reduce performance. Therefore, it is generally not a desirable approach.
A more desirable (prior art) technique to eliminate charge sharing in bulk CMOS is the use of an intermediate node precharge circuit 2 illustrated in FIG. 2(A). PFET device 155 is added between the chip power supply source Vdd 101 and the NFET stack node 160 to hold the NFET stack node 160 high as long as the input signal 150 is low. The result of this circuit modification is that, independent of the input sequencing of the clock input signal 120 and the input signal 150, the circuit 2 is immune to charge sharing and will evaluate correctly. The addition of device 155 adds some capacitive gate-loading to the input signal 150 as well as some diffusion capacitance to the NFET stack node 160, but can be made small enough to have a minimal performance impact. FIG. 3(A) shows this same technique applied to a three input clocked domino logic circuit 4.
While precharging the NFET stack node high in order to prevent charge sharing is a well established technique for bulk CMOS devices, it can cause problems for SOI CMOS circuits, which contain a parasitic bipolar device in parallel with the FET""s channel. Activating the parasitic bipolar of the top NFET in the NFET logic stack (NFET 140 in FIG. 2(A)) is a concern for dynamic circuits, as the generated current can cause the primary node 195 to be unintentionally discharged.
In FIG. 2(A), the primary node 195 is at the power supply voltage Vdd and the NFET stack node 160 is precharged by device 155 to the power supply voltage Vdd, then the body of NFET device 140 will settle to Vdd. The CLOCK input 120 remains low (circuit is not supposed to be selected) but input signal 150 pulses high, the source (collector) will be pulled to ground 170 through NFET device 130 and unintentional bipolar current will flow through NFET 140, possibly disturbing primary node 195.
The bipolar current occurs because the N-P-N transistor formed by the drain (emitter), body (base), and source (collector) of NFET stack device 140 is momentarily biased in the active gain region when the source is pulled to ground; the drain-body N-P diode is reversed-biased as the floating body of the NFET couples low with the source; and the source-body diode is forward-biased until the body couples low with the source. Because the intermediate precharge scheme of FIG. 2(A) allows the parasitic bipolar to be active, it is an undesirable circuit topology for SOI technology.
Bipolar currents can also be generated in the standard clocked domino circuit of FIG. 1. Here the primary node 95 is precharged to the power supply voltage Vdd and the NFET stack node 60 is charged to Vddxe2x88x92Vthn (NFET threshold) from a previous cycle. For an SOI circuit 1 in this instance, the body of NFET device 40 will settle to a potential between Vdd and Vddxe2x88x92Vthn, and the bipolar structure will act similarly to that described above relating to FIG. 2(A). The clock signal 20 remains low while input signal 50 pulses high, bipolar current flows through NFET device 40 and reduces the potential of the primary node 95 sufficiently to cause unintentional switching of output 98.
Fortunately for SOI technologies, the isolation of source and drain diffusions from the bulk silicon reduces the capacitance of these nodes by approximately 25%. One benefit of this reduced capacitance is that charge sharing, though still present, is of a much lower magnitude and concern, and circuit topologies can be developed to address eliminating the bipolar currents.
The intermediate precharge-low circuit 3 approach illustrated in FIG. 2(B) is a prior art technique which eliminates bipolar current concerns for domino logic. NFET stack node 260 is precharged to Vthp, where Vthp is the body-effected threshold voltage of a PFET device. In this precharged state, the body of NFET device 240 will settle to a potential between the power supply voltage Vdd and Vthp. This voltage is low enough to prevent the source-body junction from forward-biasing when the source node of NFET 240 (stack node 260) is pulled to ground. With this biasing scheme in place, if input clock signal 220 remains low while input signal 250 switches high, NFET stack node 260 will transition from Vthp to ground 270 without causing bipolar currents. The power supply voltage Vdd is shown as 201.
As with the precharge-high approach to charge-sharing, the precharge-low approach to bipolar currents imposes additional gate capacitance on the inputs and diffusion capacitance on NFET stack node 260. Similarly, PFET precharge device 255 can be made small enough to have a minimal performance impact on a two-high NFET stack 230, 240. However, there is an additional performance penalty in SOI circuits for causing the bodies of NFET devices 230 and 240 to settle to lower potentials than would in an identical circuit without precharge-low device 255.
Moreover, with the body potential of NFET device 240 between Vdd and Vthp, and the body potential of NFET device 230 between Vthp and ground 270, the threshold voltages of NFET devices 240 and 230 are significantly higher than they would be without the precharge-low device 255. Thus, these higher threshold voltages slow the discharge of the primary node 295 through the NFET stack node 260 during circuit evaluation, thereby reducing chip performance. For dynamic NFET stacks of two, this performance impact is small and far better than the consequences of having the circuit fail due to unanticipated bipolar currents. However, for dynamic NFET stacks of three or greater (as shown in FIGS. 3(B)), the performance impact of this method is substantial.
Thus, there remains a need for a new and improved dynamic logic circuit with an alternating precharge scheme, which results in a faster discharge of the primary node in the circuit, resulting in a substantial performance improvement of the chip.
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional dynamic logic circuits, the present invention has been devised, and it is an object of the present invention to provide a structure and method for a new and improved dynamic logic circuit with an alternating precharge scheme. It is another object of the present invention to provide a logic circuit, which results in a faster discharge of the primary node in the circuit. Still another object of the present invention is to provide a logic circuit, which results in a substantial improvement in the logic performance of the chip.
In order to attain the objects suggested above, there is provided, according to one aspect of the invention, a method and system for reducing bipolar current in a SOI (silicon-on-insulator) circuit comprising a first portion operatively connected to a second portion, wherein the system alternates from a precharge high mode to a precharge low mode.
Specifically, the structure for reducing bipolar current in a SOI circuit by alternating precharge low and precharge high methodologies comprises a reset signal source 500; a first PFET device 580 coupled to the reset signal source 500; a second PFET device 585 coupled to an output signal source 498; an inverter 590 coupled to the output signal source 498; a clock signal source 520; a first NFET device 540 coupled to the clock signal source 520; a third PFET device 555 coupled to the clock signal source 520; a first NFET stack node 560 coupled to the third PFET device 555; a first input signal source 551; a second NFET device 530 coupled to the first input signal source 551; a fourth PFET device 557 coupled to the first input signal source 551; a second NFET stack node 565 coupled to the fourth PFET device 557; a second input signal source 550; a third NFET device 535 coupled to the second input signal source 550; and a fifth PFET device 556 coupled to the second input signal source 550, the power supply voltage source 501, and the fourth PFET device 557.
Moreover, the clock signal source 520 causes the first NFET stack node 560 to be precharged to a body-effected threshold voltage Vthp of the third PFET device 555.
The first input signal 551 and the second input signal source 550 cause the second NFET stack node 565 to be precharged to the power supply voltage Vdd through both the fourth PFET device 557 and fifth PFET device 556. With the source region of the first NFET device 540 at Vthp and the drain region of the first NFET device 540 (primary node 595 precharged to Vdd by restore device 580) at the power supply voltage Vdd, the body potential of the first NFET device 540 will settle to a level between the power supply voltage Vdd and a body-effected threshold voltage Vthp of the third PFET device 555.
Furthermore, the body potential of the second NFET device 530 settles to a level between Vdd and Vthp, due to the fact that the second NFET device""s 530 source voltage is Vdd and it""s drain voltage is at Vthp. The first input signal source 551 causes the second NFET device 530 to have a body potential in between a body-effected threshold voltage Vthp of the fourth PFET device 557 and a power supply voltage Vdd. Likewise, the voltage of the second NFET stack node 565 results in the third NFET device 535 to have a body potential in between Vthp and ground 570.
Additionally, the first, second, and third NFET devices 540, 530, and 535, respectively, each comprise a source and drain region. Specifically, the first NFET device 540 comprises a source region 560, which is also the first NFET stack node 560; and a drain region 595, which is also the primary node 595. Similarly, the second NFET device 530 comprises a source region 565, which is also the second NFET stack node 565; and a drain region 560, which is also the first NFET stack node 560. Also, the third NFET device 535 comprises a source region 570 (ground); and a drain region 565, which is also the second NFET stack node 565.